1. Field of the Invention
The invention relates to a processor and an instruction control method of performing instruction control for holding information of a previous instruction until a following instruction is committed. More particularly, the invention relates to a processor and an instruction control method of performing instruction control for developing an instruction to a multiflow and forwarding information of a previous flow to a following flow.
2. Description of the Related Arts
Hitherto, in a processor for executing dynamic pipeline scheduling, processes are separately executed by three units: an instruction issuing unit of in-order depending on program order; an instruction executing unit of out-of-order which does not depend on the program order; and a committing unit of the in-order depending on the program order. That is, the instruction issuing unit fetches instructions by the in-order, decodes them, and allows a reservation station to hold the instruction operation (OP code) and an operand. As soon as all operands are prepared in the reservation station and an arithmetic operating unit is made usable, the instruction executing unit speculatively executes the instruction by the out-of-order and obtains a result. The committing unit discriminates commitment of the instruction on the basis of a branch prediction result or the like, completes the instruction by the in-order, and stores the execution result into a register file or a memory (only in the case of storage). In the processor using such dynamic pipeline scheduling, although a frequency is low in the program, there is an instruction kind which has to be internally multiflow developed into a plurality of instruction flows in a decoding cycle of the fetched instruction. For example, in an SPARC instruction architecture, a pixel distance instruction corresponds to such an instruction. The pixel distance instruction is an instruction to divide a pixel value of 64 bits stored in each of source registers R1 and R2 on an 8-bit unit basis, calculate differences between the values in both registers, and thereafter, obtain the sum of the differences. The pixel distance instruction is developed into a multiflow comprising a previous flow for executing a subtracting operation and a following flow for executing an adding operation in the decoding cycle, stored into the reservation station, and thereafter, the subtracting operation of the previous flow is executed by the out-of-order. An execution result is forwarded before executing the instruction of the following flow, an adding operation is executed, and an obtained result is committed. In the case of forwarding information of the previous flow to the following flow, a dedicated hardware register for holding the execution information of the previous flow has conventionally been provided.
However, if the dedicated hardware register is provided for the forward control in the multiflow of the instruction of the low frequency, it is wasteful in terms of resources. Therefore, a method whereby a register on a register update buffer (RUB) which is provided for renaming is allocated without providing the dedicated hardware register is considered. In the processor using the out-of-order, a register renaming technique has been known as a method whereby register contents are updated and referred to in the program order. The register renaming is a process such that a register on the register update buffer for holding register update data until the commitment is allocated to an arithmetic operation instruction for updating the register and a memory fetch instruction. At this time, information showing that an allocation register of the register update buffer is being updated and pending and an allocation address of the register update buffer are held in a renaming map. According to the following instruction, with reference to the address on the register update buffer corresponding to a source register of the renaming map by the address of the register serving as a reading source, when the register update is pending, the data forward is controlled by the update buffer allocation address. However, since the allocation register on the register update buffer is released by the commitment of the instruction, when there is an empty time in an interval from the commitment of the previous flow to the execution of the following flow, there is a possibility that the allocation register is broken by another subsequent instruction. There is, consequently, a problem such that the forward control for the following flow is not guaranteed.
A similar problem is also caused with respect to an instruction ID of the multiflow in a compare and swap instruction of the SPARC instruction architecture.
The compare and swap instruction is described ascas [rs1], rs2, rdand has an instruction operation such that a value of a memory is loaded by using a source register rs1 as an address and written into a destination register rd, such a value is compared with a value of a source register rs2, and if they coincide, the original destination register rd is stored into a memory whose address is equal to rs1, and if they do not coincide, the original destination register rd is not stored into the memory. The compare and swap instruction is developed into the multiflow comprising a loading of the previous flow, a comparing operation, and a store operation of the following flow into the memory. For example, if IID=x is allocated as an instruction ID to the previous flow, although an instruction ID=X +1 which has been increased by one is inherently allocated to the following flow, the instruction ID is emulated to the same instruction ID=x as that in the first flow without executing such allocation. The emulation of the instruction ID is executed to enable different entries of the incomplete previous flow and following flow stacked to a commit stack entry to be referred to as a same entry by the instruction ID=x. Thus, it is possible to control in a manner such that by referring to the comparison result held in the previous flow entry by the instruction ID=x which has been allocated to the following flow and emulated just before the execution of the following flow, if they coincide, the store operation into the memory is executed and, if they do not coincide, the result is abandoned. However, since the commit stack entry is released by the commitment of the instruction, if there is an empty time in the interval from the commitment of the previous flow to the execution of the following flow, there is a possibility that the commit stack entry of the previous flow is broken by another subsequent instruction. There is, consequently, a problem such that the emulation control for the following flow is not guaranteed.